1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and an erasing control method thereof, and in particular to a non-volatile semiconductor memory device including a plurality of memories to which information is writable and from which information is erasable, and an erasing control method thereof.
2. Description of the Related Art
Conventionally, ETOX (EPROM Thin Oxide (registered trademark of Intel Corporation)) type flash memories are most commonly used as a flash memory as an example of a non-volatile semiconductor memory device.
FIG. 16 is a schematic cross-sectional view of one of a plurality of memory cells 150 in a conventional ETOX type flash memory.
The ETOX flash memory mainly performs a read operation, a program write operation, and an erasing process including an erasing operation and a pre-erasing write operation. In the read operation, a read procedure is performed. In the program write operation, a program write procedure and a program write verification procedure are performed. In the erasing operation, an erasing procedure and an erasing verification procedure are performed. In the pre-erasing write operation, a pre-erasing write procedure and a pre-erasing write verification procedure are performed.
Each memory cell 150 has the following structure. In a surface area of a semiconductor substrate 151, a source region 152 acting as one of two driving terminals and a drain region 153 acting as the other driving terminal are provided with a prescribed interval therebetween. A region in the semiconductor substrate 151 between the source region 152 and the drain region 153 acts as a channel region 151a. A tunnel oxide layer 154, a floating gate 155, an interlayer insulating layer 156, and a control gate 157 acting as a control terminal are provided sequentially in this order on the channel region 151a of the semiconductor substrate 151 so as to cover edges of the source region 152 and the drain region 153.
Next, an operating principle of such a conventional ETOX type flash memory will be described.
Table 1 shows the voltages applied in the program write procedure, the erasing procedure, and the read procedure of the conventional ETOX type flash memory. The voltages shown in Table 1 are used when a source erasing method (described below) is used.
TABLE 1Control gateDrainSourceSubstrateProgram9 V5 V/0 V or0 V0 VwriteOpenErasing−9 V Open5 V0 VRead5 V1 V0 V0 V
As shown in Table 1, in the program write procedure, a program write voltage Vpp of 9 V is applied to the control gate 157, a reference voltage Vss of 0 V is applied to the source region 152 and the semiconductor substrate 151, and a voltage of 5 V is applied to the drain region 153.
At this point, a large magnitude of current flows in the channel region 151a between the source region 152 and the drain region 153, and hot electrons are generated in a portion in the channel region 151a closer to the drain region 153 where the level of the electric field is high. This causes electrons to be injected into the floating gate 155 of the memory cell 150, which places the memory cell 150 into a program written state. As a result, the threshold voltage of the memory cell 150 is increased. The drain region 153 of the memory cell 150 to which no writing is to be performed is supplied with 0 V or placed into an open state.
FIG. 17 is a graph illustrating a distribution of the threshold voltages of the memory cells 150 provided in a conventional binary flash memory. In FIG. 17, the horizontal axis represents the threshold voltage of the memory cells 150, and the vertical axis represents the number of memory cells 150.
Usually in a binary flash memory, the state in which electrons are injected into the floating gate 155 of the memory cell 150 is a program written state, where data is “0”. In this example, the threshold voltages of the memory cells 150 to which writing has been performed are distributed over a range higher than 5 V.
The state where electrons are pulled out from the floating gate 155 of the memory cell 150 is an erased state, where data is “1”. In this example, the threshold voltages of the memory cells 150 from which data has been erased are distributed over a range of 0.5 V to 3 V.
When the threshold voltage of the memory cell 150 increases to a prescribed level (5 V in this example) or higher, the program write operation is terminated. When the threshold voltage of the memory cell 150 decreases to a prescribed level (3 V in this example) or lower, the erasing operation is terminated.
In the erasing procedure, a voltage of Vnn of −9 V is applied to the control gate 157, a voltage Vpe of 6 V (or 5 V) is applied to the source region 152, a reference voltage Vss of 0 V is applied to the semiconductor substrate 151, and the drain region 153 is placed into an open state. This causes electrons to be pulled out from the floating gate 155 via the tunnel oxide layer 154 in a portion of the channel region 151a closer to the source region 152. As a result, the threshold voltage of the memory cell 150 is decreased. This erasing method is referred to as a “source erasing” method. The distribution of the threshold voltages of the memory cells 150 in this case is similar to that of the data “1” state (erased state) in FIG. 17.
While the erasing procedure is performed, a BTBT (Band To Band Tunneling) current flows between the source region 152 and the semiconductor substrate 151. When the BTBT current is generated, hot holes and hot electrons are both generated. The hot electrons flow to the drain region 153, while the hot holes are attracted toward, and are trapped in, the tunnel oxide layer 154. It is considered that the phenomenon that hot holes are trapped in the tunnel oxide layer 154 deteriorates the reliability of data storage.
One technique to solve this drawback is a data erasing method, which is also referred to as a channel erasing method. Table 2 shows the voltages applied in the program write procedure, the erasing procedure, the read procedure, and the pre-erasing write procedure of the conventional ETOX type flash memory when the channel erasing method is used.
TABLE 2Control gateDrainSourceSubstrateProgram9 V5 V/0 V or0 V0 VwriteOpenErasing−9 V OpenOpen6 VRead5 V1 V0 V0 VPre-erasing9 V5 V/0 V or0 V0 VwriteOpen
As shown in Table 2, in the erasing procedure, a voltage Vnn of −9 V is applied to the control gate 157, a voltage Vpe of 5 V (or 6 V) is applied to the channel region 151a (substrate), and the source region 152 and the drain region 153 are placed into an open state. This causes electrons to be pulled out from the floating gate 155 via the tunnel oxide layer 154 in a portion of the channel region 151a closer to the source region 152. As a result, the threshold voltage of the memory cell 150 is decreased. The distribution of the threshold voltages of the memory cells 150 in this case is similar to that of the data “1” state (erased state) in FIG 17. With the channel erasing method, the program write procedure and the read procedure use substantially the same voltages as those for the source erasing method shown in Table 1.
In the read procedure, 1 V to applied to the drain region 153, 5 V is applied to the control gate 157, and a reference voltage Vss of 0 V is applied to the semiconductor substrate 151 and the source region 152. When the memory cell 150 is in the erased state and thus the threshold voltage is low, a current flows in the memory cell 150. Therefore, the memory cell 150 is determined to be in the data “1” state shown in FIG. 17. When the memory cell 150 is in the program written state and thus the threshold voltage is high, no current flows in the memory cell 150. Therefore, the memory cell 150 is determined to be in the data “0” state shown in FIG. 17. Whether the memory cell 150 is in the data “1” state or in the data “0” state is determined as follows. A potential corresponding to the magnitude of the current flowing in the memory cell from which data is to be read, and a potential corresponding to the magnitude of the current flowing in a reference cell, are detected and compared by a sense amplifier. The reference cell is provided separately from the memory cell in the memory cell array and has a prescribed reference threshold voltage set therein.
Next, a sequence of an erasing process in the conventional binary flash memory will be described.
FIG. 18 in a flowchart illustrating an erasing process algorithm regarding the sequence of the erasing process in the conventional binary flash memory.
As shown in FIG. 17, the threshold voltages of the memory cells in a memory block before the erasing process are one of the two states mentioned above, i.e., the state of 0.5 V to 3 V and the state of 5 V or higher.
As shown in FIG. 18, the erasing process starts with the pre-erasing write procedure in step S1, which is performed in order to prevent excessive erasing. The pre-erasing write procedure is disclosed by, for example, Japanese Laid-Open Publication No. 9-320282. For the pre-erasing write procedure, the voltages shown in Table 2 are used. The gate voltage Vg is 9 V. The voltages for the pre-erasing write procedure are the same as those of the program write procedure. The pre-erasing write procedure is performed on all the memory cells in the memory block.
Next, in step S2, the pre-erasing write verification procedure is performed. In this procedure, a reference voltage of 5 V is used as shown in Table 3. Therefore, the pre-erasing write operation, including the pre-erasing write procedure and the pre-erasing write verification procedure, is performed until the threshold voltages of all the memory cells in the memory block become 5 V or higher.
TABLE 3ProcedureReference voltageProgram write5 VPre-erasing write5 V
When it is determined in step S3 that all the memory cells in the memory block have a threshold voltage of 5 V or higher, the pre-erasing write procedure and the pre-erasing write verification procedure are terminated.
In step S4, the erasing procedure is performed by applying an erasing pulse to all the memory cells of the memory block with the voltages shown in Table 2.
In step S5, the erasing verification procedure is performed. The reference voltage used in this procedure is 3 V in the case of FIG. 17. Therefore, the erasing procedure and the erasing verification procedure are repeated until the threshold voltages of all the memory cells in the memory block become 3 V or lower.
When it is determined in step S6 that the threshold voltages of all the memory cells in the memory block become 3 V or lower, the erasing procedure and the erasing verification procedure are terminated.
In step S7, it is checked by a software program whether or not there is a memory cell having a threshold voltage of 0.5 V or lower. When there is such a memory cell, that memory cell is adjusted to have a threshold voltage of 0.5 V or higher and 3 V or lower. The threshold voltage of the memory cell is thus controlled by the software program, and then the erasing process is terminated.
The above-described conventional erasing method has a problem in reliability of the flash memory, which is caused by the hot holes being trapped in the tunnel oxide layer as described above. This will be described in detail below.
One cause of deterioration of the reliability of the flash memory is an electric field stress on an oxide layer (e.g., the tunnel oxide layer 154) which is generated during the erasing operation. By the conventional erasing method, the threshold voltages before the erasing operation is 5 V or higher due to the pre-erasing write operation.
Assuming that the charge amount Qfg of the floating gate 155 is −1.2 V, the floating gate voltage Vfg is:Vfg=Cg×Vg+Cw×Vwell−Qfg
where Vfg: floating gate voltage;                Vg: control gate voltage;        Vwell: well voltage;        Cg: gate coupling ratio;        Cw: well coupling ratio; and        Qfg: charge amount of the floating gate.        
Therefore, the voltage Vfg of the floating gate 155 is:0.6×(−9 V)+0.2×(6 V)−1.2 V=−5.4 V.
The electric field Eox which is applied to the tunnel oxide layer 154 is:
                    Eox        =                              (                          Vwell              -              Vfg                        )                    /          Tox                                        =                                            (                              6                -                                  (                                      -                    5.4                                    )                                            )                        /                          (                                                100                  ⁢                                                                          ⁢                  E                                -                8                            )                                =                      11.4            ⁢                                                  ⁢                          MeV              .                                          
where Eox: electric field applied to the tunnel oxide layer; and                Tox: thickness of the tunnel oxide layer.        
Such an electric field stress on the tunnel oxide layer 154 is applied to all the memory cells in the memory block each time an erasing pulse is applied for the erasing procedure. As a result, holes and electrons are trapped in the tunnel oxide layer 154, which deteriorates the data retention. The strength of the data retention can be dealt using probability as reported by IEEE 40th Annual International Reliability Physics Symposium 2002, pages 7–20. As the number of memory cells receiving the electric field stress is smaller, the reliability regarding the data retention of the entire memory block and thus of the entire chip is improved.
As the memory cells, multiple bit memory cells to which 2- or more bit information is writable are known in addition to the binary memory bit to which binary (i.e., 1-bit) information is writable.
FIG. 19 is a graph illustrating the distribution of the threshold voltages of the memory cells in a conventional multiple bit flash memory. In FIG. 19, the vertical axis represents the number of memory cells, and the horizontal axis represents the threshold voltage of the memory cells.
As shown in FIG. 19, the threshold voltages of the memory cells in the memory block before the erasing operation are one of the four states, i.e., erased state (the threshold voltages are 3.0 V or lower), written state VtL (the threshold voltages are in the range of 4.0 V to 4.4 V), written state VtM (the threshold voltages are in the range of 5.0 V to 5.4 V), and written state VtH (the threshold voltages are in the range of 6.0 V to 6.4 V).
Next, an erasing algorithm of a sequence of an erasing process of a conventional quaternary flash memory will be described in detail.
FIG. 20 is a flowchart illustrating the erasing algorithm of the sequence of the erasing process of the conventional quaternary flash memory.
As shown in FIG. 20, the erasing process starts with the pre-erasing write procedure in step S31, which is performed in order to prevent excessive erasing. For the pre-erasing write procedure, the voltages shown in Table 4 (“pre-erasing write”), for example, are used. The gate voltage Vg is 9 V. A same gate voltage is used for the state having the highest threshold voltage and the state having the lowest threshold voltage. The voltages for the pre-erasing write procedure are the same as the voltages for writing information the highest threshold voltage in the program write procedure. The pre-erasing write procedure is performed on all the memory cells in the memory block. Table 4 shows the voltages applied for writing information having the highest threshold voltage in the program write procedure, the erasing procedure, the read procedure, and the pre-erasing write procedure of the conventional multiple bit flash memory when the channel erasing method is used.
TABLE 4Control gateDrainSourceSubstrateProgram6 V–9 V5 V/0 V or0 V0 VwriteOpenErasing−9 V OpenOpen6 VRead5 V1 V0 V0 VPre-erasing9 V5 V/0 V or0 V0 VwriteOpen
Next, in step S32, the verification procedure is performed for verifying the pre-erasing write. Since the reference voltage is 6 V, the above pre-erasing operation is performed until the threshold voltages of all the memory cells in the memory block become 6 V or higher.
After the pre-erasing write operation including the pre-erasing write procedure and the pre-erasing write verification procedure, the threshold voltages of the memory cells in the memory block are distributed in the range of 6 V or higher as shown in FIG. 21.
FIG. 21 is a graph illustrating a distribution of the threshold voltages of the memory cells of a conventional multiple bit flash memory after the pre-erasing write operation.
When it is determined in step S33 that all the memory cells in the memory block have a threshold voltage of 6 V or higher, the pre-erasing write procedure and the pre-erasing write verification procedure are terminated. Then, the erasing procedure is performed by applying an erasing pulse in step S34.
In step S34, an erasing pulse is applied to all the memory cells in the memory block with the voltages shown in Table 4.
Steps S35 through S37 are performed in the same manner as those for the binary flash memory. In step S35, the erasing verification procedure of verifying the erasing is performed. In step S36, it is determined whether or not the threshold voltages of all the memory cells in the memory block are 3 V or lower. The erasing procedure of applying an erasing pulse and the erasing verification procedure are repeated until the threshold voltages of all the memory cells in the memory block become 3 V or lower.
When it is determined in step S36 that the threshold voltages of all the memory cells in the memory block become 3 V or lower, the erasing procedure and the erasing verification procedure are terminated.
In step S37, it is checked by a sequence of software (software program) whether or not there is a memory cell having a threshold voltage of 0.5 V or lower. When there is such a memory cell, that memory cell is adjusted to have a threshold voltage of 0.5 V or higher and 3 V or lower. When the number of the memory cells having a threshold voltage of 0.5 V or lower becomes zero, this sequence is terminated, and the erasing process is terminated.
When an erasing pulse is applied to the memory cells having the distribution shown in FIG. 21 in the above-mentioned conventional erasing process, the charge amount Qfg of the floating gate is −1.8 V. The floating gate voltage Vfg in this case is:0.6×(−9V)+0.2×(6V)−1.8V=−6V.
The electric field Eox which is applied to the tunnel oxide layer is:(6V−(−6V))/100 Å=12 MeV.
According to this conventional art, an electric field of 12 MeV is applied to the tunnel oxide layer of all the memory calls in the memory block, and thus substantially the same electric field stress is applied to the memory cells in the erased state, the written state VtL, the written state VtM, and the written state VtH before the erasing process. This means an excessive stress is applied to at least the memory cells which were in the erased state, the written state VtL, the written state VtM before the erasing process.